Renesas H8S Series Hardware Manual page 721

T
ø
CS5 to CS2
(RAS)
CAS
ø
A to A
23 0
CS0
AS
RD
(read)
D to D
15 0
(read)
Figure 22-14 Burst ROM Access Timing (Two-State Access)
T
Rp
Rr
t
CSD2
t
CASD
Figure 22-13 Self-Refresh Timing
T T or T
1 2 3
T T
Rc
T
1
t
AD
t
AS
t
t
ASD
ASD
t
ACC3
Rev.6.00 Oct.28.2004 page 693 of 1016
Rc
t
CSD2
t
CASD
T
2
t
AH
t
RSD2
t t
RDS RDH
REJ09B0138-0600H