Renesas H8S Series Hardware Manual page 561

16-bit single-chip microcomputer

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If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore

this data can be read.

Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive

operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or

the PER and ORER flags can be used to check that the receive operation has been completed.

When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then

start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit

operation has been completed.

Fixing Clock Output Level: When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1

and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.

Figure 15-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and

the CKE0 bit is controlled.

Interrupt Operation: There are three interrupt sources in Smart Card interface mode: transmit data empty interrupt (TXI)

requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt

(TEI) request is not used in this mode.

When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.

When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship

between the operating states and interrupt sources is shown in table 15-8.

Table 15-8 Smart Card Mode Operating States and Interrupt Sources

Operating State

Data Transfer Operation by DMAC or DTC: In Smart Card mode, as with the normal SCI, transfer can be carried out

using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in

SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source,

the DMAC or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE

Specified pulse width

Figure 15-8 Timing for Fixing Clock Output Level

Specified pulse width

Not possible Not possible

Not possible Not possible

Rev.6.00 Oct.28.2004 page 533 of 1016

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