Timer Counter (Tcnt); Timer General Register (Tgr); Timer Start Register (Tstr) - Renesas H8S Series Hardware Manual

10.2.6

Timer Counter (TCNT)

Channel 0: TCNT0 (up-counter)
Channel 1: TCNT1 (up/down-counter*)
Channel 2: TCNT2 (up/down-counter*)
Channel 3: TCNT3 (up-counter)
Channel 4: TCNT4 (up/down-counter*)
Channel 5: TCNT5 (up/down-counter*)
Bit : 15 14
Initial value : 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These counters can be used as up/down-counters only in phase counting mode or when counting
overflow/underflow on another channel. In other cases they function as up-counters.
The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
10.2.7

Timer General Register (TGR)

Bit : 15 14
Initial value : 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16
TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0
and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and
in hardware standby mode.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
10.2.8

Timer Start Register (TSTR)

Bit : 7
—
Initial value : 0
R/W : —
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00
by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR,
first stop the TCNT counter.
Rev.6.00 Oct.28.2004 page 366 of 1016
REJ09B0138-0600H
13 12 11 10 9
0 0 0 0 0
13 12 11 10 9
1 1 1 1 1
6 5
— CST5 CST4
0 0
— R/W R/W
8 7 6 5 4
0 0 0 0 0
8 7 6 5 4
1 1 1 1 1
4 3 2
CST3 CST2
0 0 0
R/W R/W
3 2 1 0
0 0 0 0
3 2 1 0
1 1 1 1
1 0
CST1 CST0
0 0
R/W R/W