Renesas H8S Series Hardware Manual page 914

DMABCRH — DMA Band Control Register
DMABCRL — DMA Band Control Register
Full address mode
Bit :
:
DMABCRH
Initial value :
:
Read/Write
Rev.6.00 Oct.28.2004 page 886 of 1016
REJ09B0138-0600H
15 14 13
FAE1 FAE0 —
0 0 0
R/W R/W R/W
Reserved
Only 0 should be
written to this bit.
Channel 0 Full Address Enable
0 Short address mode
1 Full address mode
Channel 1 Full Address Enable
0 Short address mode
1 Full address mode
H'FF06
H'FF07
12 11 10
— DTA1 — DTA0
0 0 0
R/W R/W R/W R/W
Reserved
Only 0 should be
written to this bit.
Channel 0 Data Transfer Acknowledge
0 Clearing of selected internal interrupt source at time of
DMA transfer is disabled
Clearing of selected internal interrupt source at time of
1
DMA transfer is enabled
Channel 1 Data Transfer Acknowledge
0 Clearing of selected internal interrupt source at time of
DMA transfer is disabled
Clearing of selected internal interrupt source at time of
1
DMA transfer is enabled
DMAC
DMAC
9 8
—
0 0
R/W
Reserved
Only 0 should be
written to this bit.
(Continued on next page)