Renesas H8S Series Hardware Manual page 536

In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the
data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set
to 1 at this time, a transmit data empty interrupt (TXI) is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been
specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7).
[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is
started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its
state.
If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
[4] After completion of serial transmission, the SCK pin is fixed.
Figure 14-17 shows an example of SCI operation in transmission.
Serial clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Rev.6.00 Oct.28.2004 page 508 of 1016
REJ09B0138-0600H
Transfer direction
Bit 7 Bit 0
Data written to TDR
and TDRE flag
cleared to 0 in TXI
interrupt service routine
1 frame
Figure 14-17 Example of SCI Operation in Transmission
Bit 7 Bit 0 Bit 1
TXI interrupt
request generated
Bit 6 Bit 7
TEI interrupt
request generated