Renesas H8S Series Hardware Manual page 667

program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated
more than (N) times on the same bits.
Write pulse application subroutine
Sub-routine write pulse
Set PSU bit in FLMCR1
Set P bit in FLMCR1
Wait (z1) µs or (z2) µs or (z3) µs
Clear P bit in FLMCR1
Clear PSU bit in FLMCR1
Note: 7 Write Pulse Width
Number of Writes (n)
998
999
1000
Note: Use a (z3) µs write pulse for additional
programming.
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
Additional program data
area (128 bytes)
Enable WDT
Wait (y) µs
*6
*5*6
Wait (α) µs
*6
Wait (β) µs
*6
Disable WDT
End sub
Increment address
Write Time (z) µs
1 z1
2 z1
3 z1
4 z1
5 z1
6 z1
7 z2
8 z2
9 z2
10 z2
11 z2
12 z2
13 z2
. .
. .
. .
z2
z2
z2
RAM
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the
subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should
be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds.
5. A write pulse of (z1) or (z2)
program data is programmed, a write pulse of (z3)
been applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.3.6, the Flash Memory Characteristics.
Program Data Operation Chart
Original Data (D) Verify Data (V)
0
1
Additional Program Data Operation Chart
Reprogram Data (X') Verify Data (V)
0
1
Figure 19-48 Program/Program-Verify Flowchart
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) µs
*6
Store 128-byte program data in program
*4
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
*1
data area consecutively to flash memory
Sub-routine-call
See note 7 regarding pulse width
Write pulse
switching.
(z1) µs or (z2) µs
*6
Set PV bit in FLMCR1
Wait (γ) µs
*6
H'FF dummy write to verify address
Wait (ε) µs
*6
Read verify data *2
NG
Read data = verify
data?
OK
NG
6 ≥ n ?
OK
Additional program data computation
Transfer additional program data to
*4
additional program data area
Reprogram data computation
*3
Transfer reprogram data to reprogram
*4
data area
128-byte
NG
data verification
completed?
OK
Clear PV bit in FLMCR1
Wait (η) µs
*6
NG
6 ≥ n ?
OK
Sequentially write 128-byte data in
additional program data area in RAM to
*1
flash memory
Write Pulse
*6
(z3 µs additional write pulse)
NG
m = 0?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
End of programming
µs
should be applied according to the progress of programming. See note 7 for the pulse widths. When the additional
µs
should be applied. Reprogram data X' stands for reprogram data to which a write pulse has
Reprogram Data (X)
0 1 Programming completed
1 0 Programming incomplete; reprogram
0 1
1 Still in erased state; no action
Additional Program Data (Y)
0 0 Additional programming executed
Additional programming not executed
1 1
Additional programming not executed
0
Additional programming not executed
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
n ← n + 1
m = 1
NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
Programming failure
Comments
Comments
Rev.6.00 Oct.28.2004 page 639 of 1016
REJ09B0138-0600H