Renesas H8S Series Hardware Manual page 248

Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and word-
size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-
state access space.
Address bus
RD
HWR
LWR
TEND
Bus release
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the
burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is
cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the
DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues
to the end of the transfer even if the DTME bit is cleared.
Rev.6.00 Oct.28.2004 page 220 of 1016
REJ09B0138-0600H
DMA DMA
read write
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Figure 7-21 Example of Full Address Mode (Burst Mode) Transfer
DMA DMA DMA
read write read
Last transfer cycle
Burst transfer
DMA DMA
write dead
Bus release