Sequential Mode - Renesas H8S Series Hardware Manual

7.5.2

Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each
byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in
DMACR.
Table 7-6 summarizes register functions in sequential mode.
Table 7-6 Register Functions in Sequential Mode
Register
23
23 15
H'FF
15
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or
decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Rev.6.00 Oct.28.2004 page 196 of 1016
REJ09B0138-0600H
DTDIR = 0 DTDIR = 1 Initial Setting
0 Source
address
MAR
register
0 Destination
address
IOAR
register
0
Transfer counter
ETCR
Function
Destination Start address of
address transfer destination
register or transfer source
Source Start address of
address transfer source or
register transfer destination
Number of transfers Decremented every
Operation
Incremented/
decremented every
transfer
Fixed
transfer; transfer
ends when count
reaches H'0000