Renesas H8S Series Hardware Manual page 378

16-bit single-chip microcomputer

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The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The

TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in

hardware standby mode.

TMDR register settings should be made only when TCNT operation is stopped.

Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to

be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to

be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not

In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.

Rev.6.00 Oct.28.2004 page 350 of 1016

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TGRB operates normally

TGRB and TGRD used together for buffer operation

TGRA operates normally

TGRA and TGRC used together for buffer operation

Normal operation

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

(Initial value)

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