Renesas H8S Series Hardware Manual page 120

Figure 5-4 shows a block diagram of the priority decision circuit.
Interrupt source
(1) Interrupt Acceptance Control
In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Table 5-6 shows the interrupts selected in each interrupt control mode.
Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Control Mode
0
2
(2) 8-Level Control
In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt
acceptance control according to the interrupt priority level (IPR).
The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher
than the mask level.
Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2)
Interrupt Control Mode
0
2
Rev.6.00 Oct.28.2004 page 92 of 1016
REJ09B0138-0600H
Interrupt
control
mode 0
Interrupt
acceptance
control
8-level
mask control
IPR
Interrupt control mode 2
Figure 5-4 Block Diagram of Interrupt Control Operation
Interrupt Mask Bits
I
0
1
×
Selected Interrupts
All interrupts
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0).
I
Default priority
determination
I2 to I0
Selected Interrupts
All interrupts
NMI interrupts
All interrupts
Vector number
× : Don't care