Renesas H8S Series Hardware Manual page 435

Contention between TGR Read and Input Capture: If the input capture signal is generated in the T
read cycle, the data that is read will be the data after input capture transfer.
Figure 10-53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Contention between TGR Write and Input Capture: If the input capture signal is generated in the T
write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Figure 10-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 10-53 Contention between TGR Read and Input Capture
Figure 10-54 Contention between TGR Write and Input Capture
TGR read cycle
T T
1 2
TGR address
X M
M
TGR write cycle
T T
1 2
TGR address
M
M
state of a TGR
1
state of a TGR
2
Rev.6.00 Oct.28.2004 page 407 of 1016
REJ09B0138-0600H