Timer Mode Register (Tmdr) - Renesas H8S Series Hardware Manual

Channel
4
Note: This setting is ignored when channel 4 is in phase counting mode.
Channel
5
Note: This setting is ignored when channel 5 is in phase counting mode.
10.2.2

Timer Mode Register (TMDR)

Channel 0: TMDR0
Channel 3: TMDR3
Bit : 7
—
Initial value : 1
R/W : —
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit : 7
—
Initial value : 1
R/W : —
Bit 2 Bit 1
TPSC2 TPSC1
0 0
1
1 0
1
Bit 2 Bit 1
TPSC2 TPSC1
0 0
1
1 0
1
6 5
— BFB
1 0
— R/W
6 5
— —
1 0
— —
Bit 0
TPSC0 Description
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
0 Internal clock: counts on ø/1024
1 Counts on TCNT5 overflow/underflow
Bit 0
TPSC0 Description
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
0 Internal clock: counts on ø/256
1 External clock: counts on TCLKD pin input
4 3 2
BFA MD3 MD2
0 0 0
R/W R/W R/W
4 3 2
— MD3 MD2
0 0 0
— R/W R/W
(Initial value)
(Initial value)
1 0
MD1 MD0
0 0
R/W R/W
1 0
MD1 MD0
0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 349 of 1016
REJ09B0138-0600H