Renesas H8S Series Hardware Manual page 773

16-bit single-chip microcomputer
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ø
A
to A
23
0
CS0
AS
RD
(read)
D
to D
15
0
(read)
Figure 22-79 Burst ROM Access Timing (One-State Access)
ø
t
BRQS
BREQ
BACK
A
to A
,
23
0
CS7 to CS0,
AS, RD,
HWR, LWR,
CAS
T
T
or T
1
2
t
BACD
t
BZD
Figure 22-80 External Bus Release Timing
T
3
1
t
AD
t
t
t
t
ACC1
RDS
t
BRQS
Rev.6.00 Oct.28.2004 page 745 of 1016
RSD2
RDH
t
BACD
t
BZD
REJ09B0138-0600H

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