Renesas H8S Series Hardware Manual page 433

Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T
TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed.
Figure 10-49 shows the timing in this case.
ø
Address
Write signal
Counter clear
signal
TCNT
Figure 10-49 Contention between TCNT Write and Clear Operations
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T
cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10-50 shows the timing in this case.
ø
Address
Write signal
TCNT input
clock
TCNT
Figure 10-50 Contention between TCNT Write and Increment Operations
TCNT write cycle
T T
1 2
TCNT address
N H'0000
TCNT write cycle
T T
1 2
TCNT address
N M
TCNT write data
state of a TCNT write
2
Rev.6.00 Oct.28.2004 page 405 of 1016
REJ09B0138-0600H
state of a
2