Renesas H8S Series Hardware Manual page 968

TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
TCSR0 Bit
Initial value
Read/Write
TCSR1 Bit
Initial value
Read/Write
Note: Only 0 can be written to bits 7 to 5, to clear these flags.
*
Rev.6.00 Oct.28.2004 page 940 of 1016
REJ09B0138-0600H
:
7 6
CMFB CMFA
:
0 0
:
R/(W)* R/(W)*
:
7 6
CMFB CMFA
: 0 0
R/(W)* R/(W)*
:
Timer Overflow Flag
0
1
Compare Match Flag A
0
[Clearing conditions]
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0.
1
[Setting condition]
Set when TCNT matches TCORA
Compare Match Flag B
0 [Clearing conditions]
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0.
1 [Setting condition]
Set when TCNT matches TCORB
H'FFB2 8-Bit Timer Channel 0
H'FFB3 8-Bit Timer Channel 1
5 4 3
OVF ADTE OS3
0 0 0
R/(W)* R/W R/W
5 4 3
OVF — OS3
0 1 0
R/(W)* — R/W
Output Select
0 0 No change when compare match B occurs
1 0 is output when compare match B occurs
1 0 1 is output when compare match B occurs
Output is inverted when compare match B
1
occurs (toggle output)
A/D Trigger Enable (TCSR0 only)
0 A/D converter start requests by compare match A are disabled
1 A/D converter start requests by compare match A are enabled
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00)
2 1 0
OS2 OS1 OS0
0 0 0
R/W R/W R/W
2 1 0
OS2 OS1 OS0
0 0 0
R/W R/W
R/W
Output Select
0 0 No change when compare
match A occurs
1 0 is output when compare
match A occurs
1 0 1 is output when compare
match A occurs
1 Output is inverted when
compare match A
occurs (toggle output)