Renesas H8S Series Hardware Manual page 381

Bit 7
Channel IOD3
0 0
1
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1 count clock, this setting is
invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Bit 7
Channel IOB3
1 0
1
Bit 6 Bit 5 Bit 4
IOD2 IOD1 IOD0 Description
0 0 0 TGR0D is Output disabled
output
1
compare
0
1
register*
1
1 0 0
1
1 0
1
0 0 0 TGR0D is
input
1
capture
×
1
register*
× ×
1
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0 Description
0 0 0 TGR1B is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
0 0 0 TGR1B is
input
1
capture
×
1
register
× ×
1
Initial output is 0 0 output at compare match
output
1 output at compare match
2
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCD0 pin
Input capture at both edges
2
Capture input Input capture at TCNT1
source is channel count-up/count-down*
1/count clock
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCB1 pin
Input capture at both edges
Capture input Input capture at generation of
source is TGR0C TGR0C compare match/input
capture
compare match/
input capture
Rev.6.00 Oct.28.2004 page 353 of 1016
(Initial value)
1
×: Don't care
(Initial value)
×: Don't care
REJ09B0138-0600H