Renesas H8S Series Hardware Manual page 990

TGR1A—Timer General Register 1A
TGR1B—Timer General Register 1B
Bit
Initial value
Read/Write
TCR2—Timer Control Register 2
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 962 of 1016
REJ09B0138-0600H
:
15 14 13 12
:
1 1 1 1
:
R/W R/W R/W R/W
:
7 6 5
— CCLR1 CCLR0
:
0 0 0
:
— R/W R/W
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
H'FFE8
H'FFEA
11 10 9 8 7
1 1 1 1 1
R/W R/W R/W R/W R/W
H'FFF0
4 3
CKEG1 CKEG0 TPSC2
0 0
R/W R/W R/W
Time Prescaler
0 0
1
1 0
1
Note: This setting is ignored when channel 2 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 —* Count at both edges
Note: * This setting is ignored when channel 2
is in phase counting mode.
TPU1
TPU1
6 5 4 3 2
1 1 1 1 1
R/W R/W R/W R/W R/W
TPU2
2 1 0
TPSC1 TPSC0
0 0 0
R/W R/W
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
0 External clock: counts on TCLKC pin input
1 Internal clock: counts on ø/1024
1 0
1 1
R/W R/W