Renesas H8S Series Hardware Manual page 250

16-bit single-chip microcomputer
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DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7-23 shows an example of DREQ pin falling edge activated normal mode transfer.
DREQ
Address bus
DMA control
Channel
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7-23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling
for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends,
acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation
is repeated until the transfer ends.
Rev.6.00 Oct.28.2004 page 222 of 1016
REJ09B0138-0600H
DMA
Bus release
read
ø
Transfer
source
Idle
Read
Write
Request clear period
Request
Minimum of 2 cycles
[1]
[2]
[3]
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.
When the DREQ pin high level has been sampled, acceptance is resumed after the
write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request
is held.)
DMA
Bus
DMA
write
release
read
Transfer
Transfer
destination
source
Idle
Read
Write
Request clear period
Request
Minimum of 2 cycles
[4]
[5]
[6]
Acceptance resumes
DMA
Bus
write
release
Transfer
destination
Idle
[7]
Acceptance resumes

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