Section 1 Overview; Overview - Renesas H8S Series Hardware Manual

Section 1 Overview

1.1

Overview

The H8S/2357 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU,
employing Renesas proprietary architecture, and equipped with peripheral functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise,
optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The
instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating
migration from the H8/300, H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer
controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit (TPU), programmable pulse generator
(PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O
ports.
1 2
Single-power-supply flash memory (F-ZTAT* ), PROM (ZTAT* ), and masked ROM versions are available, providing a
quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with
frequently changing specifications.
The features of the H8S/2357 Group are shown in table 1-1.
Notes: 1. F-ZTAT is a trademark of Renesas Technology, Corp.
2. ZTAT is a registered trademark of Renesas Technology, Corp.
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