Renesas H8S Series Hardware Manual page 387

Bit 3
Channel IOA3
3 0
1
Bit 3
Channel IOC3
3 0
1
Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input
*
capture/output compare is not generated.
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0 Description
0 0 0 TGR3A is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
0 0 0 TGR3A is
input
1
capture
×
1
register
× ×
1
Bit 2 Bit 1 Bit 0
IOC2 IOC1 IOC0 Description
0 0 0 TGR3C is Output disabled
output
1
compare
0
1
register*
1
1 0 0
1
1 0
1
0 0 0 TGR3C is
input
1
capture
×
1
register*
× ×
1
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCA3 pin
Input capture at both edges
Capture input Input capture at TCNT4
source is channel count-up/count-down
4/count clock
Initial output is 0 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCC3 pin
Input capture at both edges
Capture input Input capture at TCNT4
source is channel count-up/count-down
4/count clock
Rev.6.00 Oct.28.2004 page 359 of 1016
(Initial value)
×: Don't care
(Initial value)
×: Don't care
REJ09B0138-0600H