Renesas H8S Series Hardware Manual page 978

TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 950 of 1016
REJ09B0138-0600H
:
7 6 5
CCLR2 CCLR1 CCLR0
:
0 0 0
:
R/W R/W R/W
Counter Clear
0
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture*
1 0 TCNT cleared by TGRD compare match/input capture*
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Notes: 1. Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
H'FFD0
4 3 2
CKEG1 CKEG0 TPSC2
0 0 0
R/W R/W R/W
Time Prescaler
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
TPU0
1 0
TPSC1 TPSC0
0 0
R/W R/W
1
2
2
1