Module Stop Mode - Renesas H8S Series Hardware Manual

21.5

Module Stop Mode

21.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a
transition is made to module stop mode. The CPU continues operating independently.
Table 21-3 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end
of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained.
After reset clearance, all modules other than DMAC and DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled.
Do not make a transition to sleep mode with MSTPCR set to H'FFFF or H'EFFF, as this will halt operation of the bus
controller.
Table 21-3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
MSTPCRH
MSTPCRL
Note: Bits 8, and 4 to 0 can be read or written to, but do not affect operation.
Bit Module
MSTP15 DMA controller (DMAC)
MSTP14 Data transfer controller (DTC)
MSTP13 16-bit timer pulse unit (TPU)
MSTP12 8-bit timer
MSTP11 Programmable pulse generator (PPG)
MSTP10 D/A converter
MSTP9 A/D converter
MSTP8 —
MSTP7 Serial communication interface (SCI) channel 2
MSTP6 Serial communication interface (SCI) channel 1
MSTP5 Serial communication interface (SCI) channel 0
MSTP4 —
MSTP3 —
MSTP2 —
MSTP1 —
MSTP0 —
Rev.6.00 Oct.28.2004 page 673 of 1016
REJ09B0138-0600H