Renesas H8S Series Hardware Manual page 897

ABWCR—Bus Width Control Register
Bit
Modes 5 to 7
Initial value
R/W
Mode 4
Initial value
Read/Write
Note: * Modes 6 and 7 are provided in the On-chip ROM version only.
ASTCR—Access State Control Register
Bit
Initial value
Read/Write
: 7 6
ABW7 ABW6
: 1 1
: R/W R/W
: 0 0
: R/W R/W
: 7 6
AST7 AST6
: 1 1
: R/W R/W
Area 7 to 0 Access State Control
0 Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1 Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
H'FED0
5 4 3
ABW5 ABW4 ABW3
1 1 1
R/W R/W R/W
0 0 0
R/W R/W R/W
Area 7 to 0 Bus Width Control
0 Area n is designated for 16-bit access
1 Area n is designated for 8-bit access
H'FED1
5 4 3
AST5 AST4 AST3
1 1 1
R/W R/W R/W
Bus Controller
2 1 0
ABW2 ABW1 ABW0
1 1 1
R/W R/W R/W
0 0 0
R/W R/W R/W
(n = 7 to 0)
Bus Controller
2 1 0
AST2 AST1 AST0
1 1 1
R/W R/W R/W
(n = 7 to 0)
Rev.6.00 Oct.28.2004 page 869 of 1016
REJ09B0138-0600H