Renesas H8S Series Hardware Manual page 240

Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address T
A
Address B
A
Legend:
Address
Address
Address
Address
Where :
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request,
burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH.
At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA
is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer
ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC.
Figure 7-15 shows the operation flow in block transfer mode.
Rev.6.00 Oct.28.2004 page 212 of 1016
REJ09B0138-0600H
Block area
T = L
A A
T = L
B B
SAID
B = L + SAIDE · (–1) · (2
A A
DAID
B = L + DAIDE · (–1) · (2
B B
L = Value set in MARA
A
L = Value set in MARB
B
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Figure 7-14 Operation in Block Transfer Mode (BLKDIR = 1)
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
DTSZ
· (N–1))
DTSZ
· (M·N–1))
Address T
1st block
2nd block
Nth block
Address B
B
B