Renesas H8S Series Hardware Manual page 971

TCNT—Timer Counter
Bit
Initial value
Read/Write
TCNT is an 8-bit readable/writable* up-counter.
Note: * TCNT is write-protected by a password to prevent accidental overwriting.
RSTCSR—Reset Control/Status Register
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
The method for writing to RSTCSR is different from that for general registers to prevent
accidental overwriting. For details see section 13.2.4, Notes on Register Access.
:
7 6
:
0 0
:
R/W R/W
For details see section 13.2.4, Notes on Register Access.
:
7 6
WOVF RSTE
:
0 0
:
R/(W)* R/W
Note: * Manual reset is not supported in the H8S/2357
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules H8S/2357 Group are not reset, but TCNT and
Watchdog Timer Overflow Flag
0
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during
watchdog timer operation
H'FFBC (W), H'FFBD (R)
5 4
0 0
R/W R/W
H'FFBE (W) , H'FFBF (R)
5 4
RSTS —
0 1
R/W —
Reset Select
0 Power-on reset
1 Manual reset*
(F-ZTAT and masked ROM versions) or the H8S/2352,
H8S/2398, H8S/2394, H8S/2392 and H8S/2390.
In these models, only 0 should be written to this bit.
TCSR in WDT are reset.
WDT
3 2 1
0 0 0
R/W R/W R/W
WDT
3 2 1
— — —
1 1 1
— — —
Rev.6.00 Oct.28.2004 page 943 of 1016
0
0
R/W
0
—
1
—
REJ09B0138-0600H