Renesas H8S Series Hardware Manual page 282

Interrupt Source
TGI5B (GR5B compare match/
input capture)
CMIA0
CMIB0
CMIA1
CMIB1
DMTEND0A (DMAC transfer end 0) DMAC
DMTEND0B (DMAC transfer end 1)
DMTEND1A (DMAC transfer end 2)
DMTEND1B (DMAC transfer end 3)
RXI0 (reception data full 0)
TXI0 (transmit data empty 0)
RXI1 (reception data full 1)
TXI1 (transmit data empty 1)
RXI2 (reception data full 2)
TXI2 (transmit data empty 2)
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
Rev.6.00 Oct.28.2004 page 254 of 1016
REJ09B0138-0600H
Origin of
Interrupt Vector
Source Number
TPU 61
channel 5
8-bit timer 64
channel 0
65
8-bit timer 68
channel 1
69
72
73
74
75
SCI 81
channel 0
82
SCI 85
channel 1
86
SCI 89
channel 2
90
Vector
Address DTCE*
H'047A DTCED4
H'0480 DTCED3
H'0482 DTCED2
H'0488 DTCED1
H'048A DTCED0
H'0490 DTCEE7
H'0492 DTCEE6
H'0494 DTCEE5
H'0496 DTCEE4
H'04A2 DTCEE3
H'04A4 DTCEE2
H'04AA DTCEE1
H'04AC DTCEE0
H'04B2 DTCEF7
H'04B4 DTCEF6
Priority
High
Low