Renesas H8S Series Hardware Manual page 145

Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0
otherwise.
Bit 4
CW2
0
1
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of
the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM
interface, these bits also select the row address to be used for comparison.
Bit 3
MXC1
0
1
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be
inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM
space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
Description
16-bit DRAM space selected
8-bit DRAM space selected
Bit 2
MXC0 Description
0 8-bit shift
•
When 8-bit access space is designated: Row address A
for comparison
•
When 16-bit access space is designated: Row address A
for comparison
1 9-bit shift
•
When 8-bit access space is designated: Row address A
for comparison
•
When 16-bit access space is designated: Row address A
for comparison
0 10-bit shift
•
When 8-bit access space is designated: Row address A
for comparison
•
When 16-bit access space is designated: Row address A
for comparison
1 —
Bit 0
RLW0 Description
0 No wait state inserted
1 1 wait state inserted
0 2 wait states inserted
1 3 wait states inserted
(Initial value)
(Initial value)
to A used
23 8
to A used
23 9
to A used
23 9
to A used
23 10
to A used
23 10
to A used
23 11
(Initial value)
Rev.6.00 Oct.28.2004 page 117 of 1016
REJ09B0138-0600H