Renesas H8S Series Hardware Manual page 923

SCKCR—System Clock Control Register
Bit
Initial value
Read/Write
ø Clock Output Control
PSTOP
MDCR—Mode Control Register
Bit
Initial value
Read/Write
Note: * Determined by pins MD
MSTPCRH — Module Stop Control Register H
MSTPCRL — Module Stop Control Register L
Bit
Initial value
Read/Write
:
7 6 5
PSTOP — —
:
0 0 0
:
R/W R/W —/(R/W)
Reserved for
H8S/2398,
H8S/2394,
H8S/2392,
and H8S/2390.
Only 0 should
be written
to this bit.
Reserved
Only 0 should be written to
this bit.
Normal Operation
0 ø output
1 Fixed high
:
7 6
— —
:
1 0
:
— —
to MD
2
MSTPCRH
:
15 14 13 12
:
0 0 1 1
:
R/W R/W R/W R/W
H'FF3A
4 3
— — SCK2
0 0
— — R/W
Bus Master Clock Select
0 0
1
1 0
1
Sleep Mode
ø output
Fixed high
H'FF3B
5 4 3
— — —
0 0 0
— — —
0
H'FF3C
H'FF3D
11 10 9 8 7
1 1 1 1 1
R/W R/W R/W R/W R/W
Specifies module stop mode
0 Module stop mode cleared
1 Module stop mode set
Clock Pulse Generator
2 1 0
SCK1 SCK0
0 0 0
R/W R/W
Bus master is in high-speed mode
0
1 Medium-speed clock is ø/2
Medium-speed clock is ø/4
0
Medium-speed clock is ø/8
1
Medium-speed clock is ø/16
0
1 Medium-speed clock is ø/32
—
—
Software Hardware
Standby Mode Standby Mode
High impedance
Fixed high
High impedance
Fixed high
MCU
2 1
MDS2 MDS1
—* —*
R R
Current mode pin operating mode
Power-Down State
Power-Down State
MSTPCRL
6 5 4 3 2
1 1 1 1 1
R/W R/W R/W R/W R/W
Rev.6.00 Oct.28.2004 page 895 of 1016
0
MDS0
—*
R
1 0
1 1
R/W R/W
REJ09B0138-0600H