Register Descriptions; Dtc Mode Register A (Mra) - Renesas H8S Series Hardware Manual

8.2

Register Descriptions

8.2.1

DTC Mode Register A (MRA)

Bit : 7
SM1
Initial value : Unde-
fined
R/W : —
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented,
decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented,
decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
MD1
0
1
Rev.6.00 Oct.28.2004 page 244 of 1016
REJ09B0138-0600H
6 5
SM0 DM1
Unde- Unde-
fined fined
— —
Bit 6
SM0 Description
— SAR is fixed
0 SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bit 4
DM0 Description
— DAR is fixed
0 DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bit 2
MD0 Description
0 Normal mode
1 Repeat mode
0 Block transfer mode
1 —
4 3 2
DM0 MD1 MD0
Unde- Unde- Unde-
fined fined fined
— — —
1 0
DTS Sz
Unde- Unde-
fined fined
— —