Renesas H8S Series Hardware Manual page 985

TCR1—Timer Control Register 1
Bit
Initial value
Read/Write
:
7 6
5
— CCLR1 CCLR0
:
0 0 0
:
— R/W R/W
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit in TSYR to 1.
H'FFE0
4 3 2
CKEG1 CKEG0 TPSC2
0 0 0
R/W R/W R/W
Time Prescaler
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Internal clock: counts on ø/256
1 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 —* Count at both edges
Note: * This setting is ignored when channel 1
is in phase counting mode.
TPU1
1 0
TPSC1 TPSC0
0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 957 of 1016
REJ09B0138-0600H