Register Configuration (On-Chip Rom Version Only) - Renesas H8S Series Hardware Manual

9.9.2

Register Configuration (On-Chip ROM Version Only)

Table 9-15 shows the port B register configuration.
Table 9-15 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR) (On-Chip ROM Version Only)
Bit : 7
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value : 0
R/W : W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR
cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Mode 6
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the
pin an input port.
• Modes 4 and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Port B Data Register (PBDR) (On-Chip ROM Version Only)
Bit : 7
PB7DR
Initial value : 0
R/W : R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software
standby mode.
Rev.6.00 Oct.28.2004 page 308 of 1016
REJ09B0138-0600H
6 5
0 0
W W W
6 5
PB6DR PB5DR PB4DR
0 0
R/W R/W R/W
Abbreviation R/W
PBDDR W
PBDR R/W
PORTB R
PBPCR R/W
4 3 2
0 0 0
W W
4 3 2
PB3DR PB2DR
0 0 0
R/W R/W
Initial Value Address *
H'00 H'FEBA
H'00 H'FF6A
Undefined H'FF5A
H'00 H'FF71
1 0
0 0
W W
1 0
PB1DR PB0DR
0 0
R/W R/W
to PB ). PBDR is initialized to
7 0