Renesas H8S Series Hardware Manual page 725

ø
A to A
23 0
CS7 to CS0
AS
RD
(read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
DACK0, DACK1
Figure 22-19 DMAC Single Address Transfer Timing (Three-State Access)
ø
TEND0, TEND1
Figure 22-20 DMAC TEND Output Timing
ø
DREQ0, DREQ1
Figure 22-21 DMAC DREQ Intput Timing
T T
1 2
t
DACD1
T T
1 2
t
TED
t
t
DRQS
DRQH
T
3
t
DACD2
or T
3
t
TED
Rev.6.00 Oct.28.2004 page 697 of 1016
REJ09B0138-0600H