Usage Notes - Renesas H8S Series Hardware Manual

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6-
33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD
signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
In the initial state after reset release, idle cycle insertion (b) is set.
ø
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
6.8.2

Usage Notes

When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between
different areas, for example, if the second access is a DRAM access, only a T
timing in this case is shown in figure 6-34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this
case is shown in figures 6-35 (a) and (b).
Bus cycle A Bus cycle B
T T T T
1 2 3 1
(a) Idle cycle not inserted
(ICIS1 = 0)
Figure 6-33 Relationship between Chip Select (CS) and Read (RD)
T
2
ø
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A Bus cycle B
T T T T T
1 2 3 I 1
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
cycle is inserted, and a T
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T
2
cycle is not. The
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