Renesas H8S Series Hardware Manual page 45

Type Symbol
Address bus A to
23
A
0
Data bus D to
15
D
0
CS7 to
Bus control
CS0
AS
RD
HWR
LWR
CAS
WAIT
LCAS
DREQ1,
DMA controller
DREQ0
(DMAC)
TEND1,
TEND0
DACK1,
DACK0
Pin No.
TFP-120 FP-128B I/O
28 to 25, 32 to 29, Output Address bus: These pins output an
23 to 16, 27 to 20,
14 to 7, 18 to 11,
5 to 2 9 to 6
51 to 48, 57 to 54, I/O
46 to 39, 52 to 45,
37 to 34 43 to 40
120 to 117 128, 127, Output Chip select: Signals for selecting
61, 60, 69, 66,
30, 29 34, 33,
2, 1
82 90 Output Address strobe: When this pin is
83 91 Output Read: When this pin is low, it
84 92 Output High write/write enable:
85 93 Output Low write:
116 126 Output Upper column address
86 94 Input
86 94 Output Lower column address strobe: The
62, 60 70, 66 Input
63, 61 71, 69 Output DMA transfer end 1 and 0: These
112, 111 122, 121 Output DMA transfer acknowledge 1 and
Name and Function
address.
Data bus: These pins constitute a
bidirectional data bus.
areas 7 to 0.
low, it indicates that address output
on the address bus is enabled.
indicates that the external address
space can be read.
A strobe signal that writes to external
space and indicates that the upper
half (D to D ) of the data bus is
15 8
enabled.
The 2CAS type DRAM write enable
signal.
A strobe signal that writes to external
space and indicates that the lower
half (D to D ) of the data bus is
7 0
enabled.
strobe/column address strobe:
The 2CAS type DRAM upper column
address strobe signal.
Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
2-CAS type DRAM lower column
address strobe signal
DMA request 1 and 0: These pins
request DMAC activation.
pins indicate the end of DMAC data
transfer.
0: These are the DMAC single
address transfer acknowledge pins.
Rev.6.00 Oct.28.2004 page 17 of 1016
REJ09B0138-0600H