Operation; Overview - Renesas H8S Series Hardware Manual

8.3

Operation

8.3.1

Overview

When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to memory. Pre-storage of
register information in memory makes it possible to transfer data over any required number of channels. Setting the
CHNE bit to 1 makes it possible to perform a number of transfers with a single activation.
Figure 8-2 shows a flowchart of DTC operation.
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination
address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed.
Table 8-2 outlines the functions of the DTC.
Start
Read DTC vector
Read register information
Data transfer
Write register information
CHNE=1
No
Transfer Counter= 0
or DISEL= 1
No
Clear an activation flag
End
Figure 8-2 Flowchart of DTC Operation
Next transfer
Yes
Yes
Clear DTCER
Interrupt exception
handling
Rev.6.00 Oct.28.2004 page 249 of 1016
REJ09B0138-0600H