Usage Notes - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and

at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the

pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode.

Notes: Phase difference and overlap

Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it

matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual

counter frequency is given by the following formula:

: Counter frequency

ø : Operating frequency

N : TGR set value

Rev.6.00 Oct.28.2004 page 404 of 1016

REJ09B0138-0600H

: 1.5 states or more

: 2.5 states or more