Transition Timing; Usage Note - Renesas H8S Series Hardware Manual

6.10.4

Transition Timing

Figure 6-37 shows the timing for transition to the bus-released state.
ø
Address bus
Data bus
AS
RD
HWR, LWR
BREQ
BACK
BREQO *
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
6.10.5

Usage Note

When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts.
Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep
mode.
CPU cycle
T T
0 1
Address
Minimum
1 state
[1]
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
Figure 6-37 Bus-Released State Transition Timing
External bus released state
T
2
High impedance
High impedance
High impedance
High impedance
High impedance
[2] [3]
state.
2
CPU
cycle
[4] [5] [6]
Rev.6.00 Oct.28.2004 page 161 of 1016
REJ09B0138-0600H