Renesas H8S Series Hardware Manual page 388

Bit 3
Channel IOA3
4 0
1
Bit 3
Channel IOA3
5 0
1
Rev.6.00 Oct.28.2004 page 360 of 1016
REJ09B0138-0600H
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0 Description
0 0 0 TGR4A is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
0 0 0 TGR4A is
input
1
capture
×
1
register
× ×
1
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0 Description
0 0 0 TGR5A is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
×
0 0 TGR5A is
input
1
capture
×
1
register
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCA4 pin
Input capture at both edges
Capture input Input capture at generation of
source is TGR3A TGR3A compare match/input
compare match/ capture
input capture
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCA5 pin
Input capture at both edges
(Initial value)
×: Don't care
(Initial value)
×: Don't care