Renesas H8S Series Hardware Manual page 7

I t e m
1.1 Overview
Table 1-1 Overview
4.1.3 Exception Vector Table
6.6.1 When DDS = 1
Figure 6-28 DACK Output Timing
when DDS = 1 (Example of DRAM
Access)
6.6.2 When DDS = 0
Figure 6-29 DACK Output Timing
when DDS = 0 (Example of DRAM
Access)
6.8.2 Usage Notes
Figure 6-35(a) Example of Idle Cycle
Operation in RAS Down Mode (ICIS1
= 1)
Figure 6-35(b) Example of Idle Cycle
Operation in RAS Down Mode (ICIS0
= 1)
Main Revisions for This Edition
P a g e Revision (See Manual for Details)
5 Product lineup
HD64F2398F20T*
F-ZTAT
Version*
Note 3 added as follows
Note: 3. For the HD64F2398F20T and HD64F2398TE20T only, the
maximum number of times the flash memory can be reprogrammed is
1,000.
72 Description amended
In modes 6 and 7 the on-chip ROM ...In this case, clearing the EAE
bit in BCRL enables the 128-kbyte (256-kbytes)* area comprising
address H'000000 to H'01FFFF (H'03FFFF)* to be used.
149 Figure 6-28 amended
150 Figure 6-29 amended
156 Figure 6-35(a) amended
Figure 6-35(b) amended
3
and HD64F2398TE20T*
5V version
HD64F2357F20 HD64F2398F20
HD64F2357TE20 HD64F2398TE20
HD64F2398F20T *
HD64F2398TE20T*
HWR, (WE)
Write
D to D
15 0
HWR, (WE)
Write
D to D
15 0
External read
T T T
I 1 2
External read
T T T
I 1 2
Rev.6.00 Oct.28.2004 page iii of xxiv
3
added
3
3
DRAM
T T
3 cI
DRAM
T T
3 cI
REJ09B0138-0600H