Register Configuration - Renesas H8S Series Hardware Manual

8.1.3

Register Configuration

Table 8-1 summarizes the DTC registers.
Table 8-1 DTC Registers
Name
DTC mode register A
DTC mode register B
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
DTC enable registers
DTC vector register
Module stop control register
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external
space. When the DTC is used, do not clear the RAME bit in SYSCR to 0.
Abbreviation R/W
2
MRA —*
2
MRB —*
2
SAR —*
2
DAR —*
2
CRA —*
2
CRB —*
DTCER R/W
DTVECR R/W
MSTPCR R/W
Initial Value Address*
3
Undefined —*
3
Undefined —*
3
Undefined —*
3
Undefined —*
3
Undefined —*
3
Undefined —*
H'00 H'FF30 to H'FF35
H'00 H'FF37
H'3FFF H'FF3C
Rev.6.00 Oct.28.2004 page 243 of 1016
1
REJ09B0138-0600H