Renesas H8S Series Hardware Manual page 849

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the
above instruction with an 8-bit bus, using three-state access with no wait states.
ø
Address bus
RD
HWR, LWR
R:W 2nd
Fetching Fetching
3rd byte 4th byte
of instruction of instruction
Figure A-1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
High level
Internal
R:W EA
operation
Fetching
1nd byte of
instruction at
jump address
Rev.6.00 Oct.28.2004 page 821 of 1016
Fetching
2nd byte of
instruction at
jump address
REJ09B0138-0600H