Renesas H8S Series Hardware Manual page 225

Figure 7-3 illustrates operation in sequential mode.
Address T
Address B
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and
when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt
request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI
transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A
interrupts. External requests can be set for channel B only.
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)
Where : L = Value set in MAR
Figure 7-3 Operation in Sequential Mode
DTID DTSZ
• (2 • (N–1))
N = Value set in ETCR
Rev.6.00 Oct.28.2004 page 197 of 1016
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