When Dds = 0; Burst Rom Interface; Overview - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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When DDS = 0

When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The

DACK output goes low from the T

In modes other than DMAC single address mode, burst access can be used when accessing DRAM space.

Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0.

Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access)

With the H8S/2357 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can

be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be

accessed at high speed.

Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a

maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for

burst access.

Rev.6.00 Oct.28.2004 page 150 of 1016

REJ09B0138-0600H

state in the case of the DRAM interface.

CAS, (UCAS),

LCAS, (LCAS)

Note: n = 2 to 5