Normal Mode - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by

setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0.

In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is

executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination

Table 7-10 summarizes register functions in normal mode.

Table 7-10 Register Functions in Normal Mode

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Transfer count register A

MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits.

MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed.

Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB.

The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and

when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt

request is sent to the CPU or DTC.

The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

Source address

address register

Transfer counter Number of transfers Decremented every

Initial Setting

Start address of

Incremented/decremented

transfer source

every transfer, or fixed

Start address of

Incremented/decremented

transfer destination

every transfer, or fixed

transfer; transfer ends

when count reaches

Rev.6.00 Oct.28.2004 page 207 of 1016

REJ09B0138-0600H