Renesas H8S Series Hardware Manual page 878

TMDR3—Timer Mode Register 3
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 850 of 1016
REJ09B0138-0600H
: 7 6
— —
: 1 1
: — —
Buffer Operation B
H'FE81
5 4 3
BFB BFA MD3
0 0 0
R/W R/W R/W
Buffer Operation A
0 TGRA operates normally
TGRA and TGRC used together
1
for buffer operation
0 TGRB operates normally
TGRB and TGRD used together
1
for buffer operation
TPU3
2 1 0
MD2 MD1 MD0
0 0 0
R/W R/W R/W
Mode
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
× × ×
1 —
Notes: 1.
MD3 is a reserved bit. In a write,
it should always be written with 0.
2.
Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written
to MD2.
× : Don't care