Renesas H8S Series Hardware Manual page 308

P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. As the PPG, TPU, and 8-bit timer are initialized by a manual reset*, the pin states
are determined by the P2DDR and P2DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 2 Data Register (P2DR)
Bit : 7
P27DR
Initial value : 0
R/W : R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2
P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 2 Register (PORT2)
Bit : 7
P27
Initial value : —*
R/W : R
Note: * Determined by state of pins P2
PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2
pins (P2 to P2 ) must always be performed on P2DR.
7 0
If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while
P2DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and
P2DR are initialized. PORT2 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 280 of 1016
REJ09B0138-0600H
6 5
P26DR P25DR P24DR
0 0
R/W R/W R/W
6 5
P26 P25 P24
—* —* —*
R R
to P2 .
7 0
4 3 2
P23DR P22DR
0 0 0
R/W R/W
4 3 2
P23 P22
—* —*
R R R
1 0
P21DR P20DR
0 0
R/W R/W
to P2 ).
7 0
1 0
P21 P20
—* —*
R R