Renesas H8S Series Hardware Manual page 298

Port 1 Data Direction Register (P1DDR)
Bit : 7
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value : 0
R/W : W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR
cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an
input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. As the PPG, TPU, and DMAC are initialized by a manual reset*, the pin states are
determined by the P1DDR and P1DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 1 Data Register (P1DR)
Bit : 7
P17DR
Initial value : 0
R/W : R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P1
P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 1 Register (PORT1)
Bit : 7
P17
Initial value : —*
R/W : R
Note: * Determined by state of pins P1
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1
pins (P1 to P1 ) must always be performed on P1DR.
7 0
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while
P1DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and
P1DR are initialized. PORT1 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 270 of 1016
REJ09B0138-0600H
6 5
0 0
W W W
6 5
P16DR P15DR P14DR
0 0
R/W R/W R/W
6 5
P16 P15 P14
—* —* —*
R R
to P1 .
7 0
4 3 2
0 0 0
W W
4 3 2
P13DR P12DR
0 0 0
R/W R/W
4 3 2
P13 P12
—* —*
R R R
1 0
0 0
W W
1 0
P11DR P10DR
0 0
R/W R/W
to P1 ).
7 0
1 0
P11 P10
—* —*
R R