Renesas H8S Series Hardware Manual page 646

φ
V
CC
FWE
MD to MD
2 0
RES
SWE bit
Flash memory access disabled period
(x: Wait time after SWE setting)
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
Notes: 1.
2.
3.
Rev.6.00 Oct.28.2004 page 618 of 1016
REJ09B0138-0600H
Programming and
Wait time: x erase possible
t
OSC1
t
MDS
t
MDS
SWE set
1 Boot mode
Mode switching *
*
In transition to the boot mode and transition from the boot mode to another mode,
mode switching via RES input is necessary.
During this switching period (period during which a low level is input to the RES pin),
the state of the address dual port and bus control output signals (AS,RD,WR) changes.
Therefore, do not use these pins as output signals during this switching period.
When making a transition from the boot mode to another mode, the mode programming
setup time t (min)= 200 ns relative to the RES clear timing is necessary.
MDS
See section 22.7.6, Flash Memory Characteristics.
Figure 19-35 Mode Transition Timing
(Example: Boot mode → User mode ↔ User program mode)
Programming
and
erase
Wait time: x possible
min 0µs
2
*
t
MDS
t
RESW
SWE clear
Mode
User User program mode
1
switching *
mode
3
Wait Programming and Wait
time: x erase possible time: x
User
User
program
mode
mode
Programming
and
erase
possible