Block Diagram - Renesas H8S Series Hardware Manual

6.1.2

Block Diagram

Figure 6-1 shows a block diagram of the bus controller.
CS0 to CS7
External bus control signals
BREQ
BACK
BREQO
WAIT
External DRAM
signals
Area decoder
Bus controller
Wait controller
DRAM controller
Bus arbiter
Figure 6-1 Block Diagram of Bus Controller
ABWCR
ASTCR
BCRH
BCRL
WCRH
WCRL
MCR
DRAMCR
RTCNT
RTCOR
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Rev.6.00 Oct.28.2004 page 105 of 1016
Internal
address bus
Internal control
signals
Bus mode signal
REJ09B0138-0600H