Renesas H8S Series Hardware Manual page 253

Figure 7-26 shows an example of DREQ level activated block transfer mode transfer.
DREQ
Address bus
DMA control
Channel
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
[1]
edge of ø, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7-26 Example of DREQ Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle,
acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer
ends.
DMA
Bus release
read
ø
Transfer
source
Idle Read Write
Request clear period
Request
Minimum of 2 cycles
[1] [2] [3]
1 block transfer
DMA DMA Bus
right dead release
Transfer
destination
Dead Idle Read
Request
Minimum of 2 cycles
[4] [5] [6]
Acceptance resumes
1 block transfer
DMA DMA DMA
read right dead release
Transfer Transfer
source destination
Write Dead Idle
Request clear period
[7]
Acceptance resumes
Rev.6.00 Oct.28.2004 page 225 of 1016
Bus
REJ09B0138-0600H